Training on Digital Design Using Verilog HDL

Chapter 1: Introduction to Digital Systems (8 hours)

1. Introduction of SOC model. (1 hr)
2. Boolean algebra and glitch analysis. (1 hr)
3. Removal of glitch using k-maps. (0.5 hr)
4. A generic approach to design sequential circuits. (2.5 hr)
5. Analysis of asynchronous circuits. (1 hr)
6. Designing of FSM based systems. (2 hr)

Chapter 2: FIFO, clock domains, timing concepts (3 hours)

1. Design of FIFO and its applications. (1.5 hrs)
2. Setup time and hold time concepts. (1.5 hrs)

Chapter 3: Verilog HDL: (24 hours)

1. Introduction to Verilog HDL. (1 hrs)
2. Data types. (1 hrs)
3. (1 hrs)
4. Conditional statements. (2 hrs)
5. Tasks and functions. (1 hrs)
6. Gatelevel modeling. (1 hrs)
7. Dataflow modeling. (2 hrs)
   1. Assign statement
   2. Delays
   3. Designing combinational circuits using dataflow modeling
8. Behavioral modeling. (7 hrs)
   1. Initial and always blocks
   2. Blocking and Non-Blocking statements
   3. Designing combinational and sequential circuits using dataflow modeling
9. Structural modeling. (3 hrs)
10. Writing test bench using Verilog HDL. (3 hrs)
11. Synthesizable and non-synthesizable constructs in Verilog HDL. (2 hrs)

Chapter 4: Synthesis: (7 hours)

1. Introduction to synthesis of Verilog HDL. (1 hr)
2. Understanding technology library. (1 hr)
3. Performing Area-Power-Timing analysis using open source (Yosys) tools. (5 hrs)

Chapter 5: FSM based digital design (3 hours)

1. Design of sequence detector using Verilog (1.5 hrs)
2. Case study of AMBA BUS(1.5 hrs)